Integrated circuits are widely used in consumer and commercial applications. Integrated circuits are generally fabricated from monocrystalline silicon. As the integration density of integrated circuits continues to increase, it generally is of increasing importance to provide high-quality monocrystalline semiconductor material for integrated circuits. Integrated circuits are typically produced by fabricating a large ingot of monocrystalline silicon, slicing the ingot into wafers, performing numerous microelectronic fabrication processes on the wafers and then dicing the wafers into individual integrated circuits that are packaged. Because the purity and crystallinity of the silicon ingot can have a large impact on the performance of the ultimate integrated circuit devices that are fabricated therefrom, increased efforts have been made to fabricate ingots and wafers with reduced numbers of defects.
Conventional methods of manufacturing monocrystalline silicon ingots will now be described. An overview of these methods is provided in Chapter 1 of the textbook "Silicon Processing for the VLSI Era, Volume 1, Process Technology", by Wolf and Tauber, 1986, pp. 1-35, the disclosure of which is hereby incorporated herein by reference. In manufacturing monocrystalline silicon, electronic grade polysilicon is converted into a monocrystalline silicon ingot. Polycrystalline silicon such as quartzite is refined to produce electronic grade polycrystalline silicon. The refined electronic grade polycrystalline silicon is then grown into a single crystal ingot using the Czochralski (CZ) or Float Zone (FZ) technique. Since the present invention relates to manufacturing a silicon ingot using the CZ technique, this technique will now be described.
CZ growth involves crystalline solidification of atoms from a liquid phase at an interface. In particular, a crucible is loaded with a charge of electronic grade polycrystalline silicon and the charge is melted. A seed crystal of silicon of precise orientation tolerances is lowered into the molten silicon. The seed crystal is then withdrawn at a controlled rate in the axial direction. Both the seed crystal and the crucible are generally rotated during the pulling process, in opposite directions.
The initial pull rate is generally relatively rapid so that a thin neck of silicon is produced. Then, the melt temperature is reduced and stabilized so that the desired ingot diameter can be formed. This diameter is generally maintained by controlling the pull rate. The pulling continues until the charge is nearly exhausted, at which time a tail is formed.
FIG. 1 is a schematic diagram of a CZ puller. As shown in FIG. 1, the CZ puller 100 includes a furnace, a crystal pulling mechanism, an environment controller and a computer-based control system. The CZ furnace is generally referred to as a hot zone furnace. The hot zone furnace includes heating elements 102 and 104, an inner crucible 106 which may be made of quartz, an outer crucible 108 which may be made of graphite and a rotation shaft 110 that rotates in a first direction 112 as shown. A hot shield 114 may provide additional thermal distribution.
The crystal pulling mechanism includes a crystal pulling shaft 120 which may rotate in direction 122 opposite direction 112 as shown. Crystal pulling shaft 120 holds seed crystal 124, which is pulled from molten polysilicon charge 126 in crucible 106 to form ingot 128.
The ambient control system may include the chamber enclosure 130, a cooling port 132 and other flow controllers and vacuum exhaust systems that are not shown. A computer-based control system may be used to control the heating elements, puller and other electrical and mechanical elements.
In order to grow a monocrystalline silicon ingot, the seed crystal 124 is contacted to the molten silicon charge 126 and is gradually pulled in the axial direction (up). Cooling and solidification of the molten silicon charge 126 into monocrystalline silicon occurs at the interface 130 between the ingot 128 and the molten silicon 126.
Real silicon ingots differ from ideal monocrystalline ingots because they include imperfections or defects. These defects are undesirable in fabricating integrated circuit devices. These defects may be generally classified as point defects or agglomerates (three-dimensional defects). Point defects are of two general types: vacancy point defects and interstitial point defects. In a vacancy point defect, a silicon atom is missing from one of its normal positions in the silicon crystal lattice. This vacancy gives rise to a vacancy point defect. On the other hand, if an atom is found at a non-lattice site (interstitial site) in the silicon crystal, it gives rise to an interstitial point defect.
Point defects are generally formed at the interface 130 between the molten silicon 126 and the solid silicon 128. However, as the ingot 128 continues to be pulled, the portion that was at the interface begins to cool. During cooling, diffusion of vacancy point defects and interstitial point defects may cause defects to coalesce and form vacancy agglomerates or interstitial agglomerates. Agglomerates are three-dimensional (large) structures that arise due to coalescence of point defects. Interstitial agglomerates are also referred to as dislocation defects or D-defects. Agglomerates are also sometimes named by the technique that is used to detect these defects. Thus, vacancy agglomerates are sometimes referred to as Crystal-Originated Particles (COP), Laser Scattering Tomography (LST) defects or Flow Pattern Defects (FPD). Interstitial agglomerates are also known as Large Dislocation (L/D) agglomerates. A discussion of defects in monocrystalline silicon is provided in Chapter 2 of the above-mentioned textbook by Wolf and Tauber, the disclosure of which is hereby incorporated herein by reference.
It is known that many parameters may need to be controlled in order to grow a high purity ingot having low numbers of defects. For example, it is known to control the pull rate of the seed crystal and the temperature gradients in the hot zone structure. Voronkov's Theory found that the ratio of V to G (referred to as V/G) can determine the point defect concentration in the ingot, where V is the pull rate of the ingot and G is the temperature gradient of the ingot-melt interface. Voronkov's Theory is described in detail in "The Mechanism of Swirl Defects Formation in Silicon" by Voronkov, Journal of Crystal Growth, Vol. 59, 1982, pp. 625-643.
An application of Voronkov's Theory may be found in a publication by the present inventor et al. entitled "Effect of Crystal Defects on Device Characteristics", Proceedings of the Second International Symposium on Advanced Science and Technology of Silicon Material, Nov. 25-29, 1996, p. 519. At FIG. 15, reproduced herein as FIG. 2, a graphical illustration of vacancy and interstitial concentrations, as a function of V/G is shown. Voronkov's Theory shows that the generation of vacancy/interstitial mixture in a wafer is determined by V/G. More particularly, for V/G ratios below a critical ratio, an interstitial rich ingot is formed, while for V/G ratios above the critical ratio, a vacancy rich ingot is formed.
Notwithstanding many theoretical investigations by physicists, material scientists and others, and many practical investigations by CZ puller manufacturers, there continues to be a need to reduce the defect density in monocrystalline silicon wafers. The ultimate need is for pure silicon wafers that are free of vacancy and interstitial agglomerates.